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Lattice Semiconductor
Functional Description
Data Type
The Viterbi Decoder IP supports two commonly used binary representations, namely, sign-magnitude and
unsigned offset, for soft decision data. In sign-magnitude representation, the most significant bit is a sign bit and
the rest of the bits represent the magnitude. The most positive number corresponds to strong logic zero and other
positive numbers are weak logic zeros. The most negative number corresponds to strong logic one and other neg-
ative numbers are weak logic ones. In unsigned offset representation, there is no sign bit in the number and all
numbers are treated positive. The smallest number (all zeros) corresponds to strong logic zero and the biggest
number (all ones) corresponds to strong logic one. The smaller numbers counting up from zero are progressively
weaker logic zeros and bigger numbers counting down from the biggest number are progressively weaker logic
ones.
Table 2-2 shows the data values and their interpretation in “Signed” and “Unsigned” data type configurations when
Soft Width is 3.
Table 2-2. Interpretation of Signed and Unsigned Data
Signed Binary
Unsigned Offset
Data
Interpretation
Data
Interpretation
111
110
101
100
000
001
010
011
-3
-2
-1
-0
0
1
2
3
(strong logic 1)
(weaker logic 1s)
(weaker logic 0s)
(strong logic 0)
111
110
101
100
011
010
001
000
7
6
5
4
3
2
1
0
(strong logic 1)
(weaker logic 1s)
(weaker logic 0s)
(strong logic 0)
Signal Descriptions
The top level interface diagram of the Viterbi Decoder is shown in Figure 2-1. The details of the I/O ports are sum-
Table 2-3. Top Level I/O Interface
Port
clk
rstn
pbstart
ibstart
Bits
1
1
1
1
I/O
I
I
I
I
Description
System clock
System wide asynchronous active-low reset signal
“Punctured block start” signal to indicate the start of a new block of punctured
data. This signal is not available while decoding non-punctured codes.
Input block start signal. This must be pulled high when the first data of a block is
applied on the input port. This port is available for block decoding only.
Input block end signal. This signal must be pulled high to indicate the last data
ibend
1
I
of a block being applied on the input port. This port is available for block decod-
ing only.
din0, din1,
Data input buses – The buses become one bit inputs for hard decision decoding
din2, din3,
din4, din5,
din6
inrate
outrate
1 or 3
to 8 (each)
1-4
2-5
I
I
I
and equals to the soft width for soft decision decoding. The number of buses is 1
for punctured codes and n for non-punctured codes, where n is the code rate
factor, from 2 to 7.
Input rate of the convolutional code for next block. This port is available only in
dynamic puncturing mode.
Output rate of the convolutional code for next block. This port is available only in
dynamic puncturing mode.
IPUG32_02.7, June 2010
12
Block Viterbi Decoder User’s Guide
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相关PDF资料
VTERB-DECO-XP-N1
IP CORE VITERBI DECODER XPGA
VTP110F
POLYSWITCH PTC RESET 1.1A STRAP
VTP175LF
POLYSWITCH PTC RESET 1.75A STRAP
VTP210GF
POLYSWITCH PTC RESET 2.1A STRAP
VTP210SF
POLYSWITCH PTC RESET 2.1A STRAP
W51-A121B1-10
CIRCUIT BREAKER THERM 10A ILLUM
W54-XC2A4B10-40
CIRCUIT BREAKER THERMAL 40AMP
WV-089047-10-9
LABEL ID PRODUCTS
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